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authorMartin Roth <martin@coreboot.org>2019-10-23 21:44:42 -0600
committerMartin Roth <martinroth@google.com>2019-10-27 18:12:50 +0000
commit468d02cc82151366a2781c9af29e6737105495cb (patch)
treede8540c053517a4da8b00ea95f24579bd9223dcd /src/northbridge/intel/gm45
parent36fcc85be459ec175c7f4be08db7ae9708f01b5d (diff)
downloadcoreboot-468d02cc82151366a2781c9af29e6737105495cb.tar.xz
src/[northbridge,security]: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/raminit.c2
-rw-r--r--src/northbridge/intel/gm45/raminit_read_write_training.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 7a30b761c5..a2c7643fb0 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -175,7 +175,7 @@ void get_gmch_info(sysinfo_t *sysinfo)
printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt);
}
- const unsigned max_fsb = (capid >> 28) & 0x3;
+ const unsigned int max_fsb = (capid >> 28) & 0x3;
switch (max_fsb) {
case 1:
sysinfo->max_fsb_mhz = 1067;
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 3f5dbca8fc..8b1e29287d 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -22,7 +22,7 @@
typedef struct {
u32 addr[RANKS_PER_CHANNEL];
- unsigned count;
+ unsigned int count;
} address_bunch_t;
/* Read Training. */