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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-25 11:40:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-11 08:57:41 +0100
commita6ac1877316216c8c56a9ab04b9ac3cde6ab01aa (patch)
tree68b39f9c23f7c6bd9ac19c2daa75f58ae057f1e8 /src/northbridge/intel/gm45
parent823020d56be1bf6425b4e433a1f1c2bbc2c4c90b (diff)
downloadcoreboot-a6ac1877316216c8c56a9ab04b9ac3cde6ab01aa.tar.xz
intel/gm45: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/northbridge.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index aaa6749a89..af62f12ad0 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -216,28 +216,11 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = 0,
};
-
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
-#if CONFIG_HAVE_ACPI_RESUME
- switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) {
- case SKPAD_NORMAL_BOOT_MAGIC:
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type = 0;
- break;
- case SKPAD_ACPI_S3_MAGIC:
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type = 3;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type = 0;
- break;
- }
-#endif
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}