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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-12-19 07:47:52 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:49:29 +0000 |
| commit | ba9b504ec5d8bc42f56cb085749c1296b1291ba9 (patch) | |
| tree | e8a52663d7b6add1437fe474986e88e5f90d53d4 /src/northbridge/intel/gm45 | |
| parent | 361a935332489c635192b39204c7ec7af1667c8f (diff) | |
| download | coreboot-ba9b504ec5d8bc42f56cb085749c1296b1291ba9.tar.xz | |
src: Replace min/max() with MIN/MAX()
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a2c7643fb0..b1da177281 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <commonlib/helpers.h> #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -436,7 +436,7 @@ static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo, unsigned int clock = 8000 / tCKmin; if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { - int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); + int new_clock = MIN(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", clock, new_clock); clock = new_clock; |