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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-14 12:55:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:58:59 +0000
commit274dabd7a04b18bc2f2378bb9faa7416dfd0ab83 (patch)
treea53f87b1200b13ced01afccd389963bb8e7c6d81 /src/northbridge/intel/gm45
parent45b79be9c06ccc925eeb3c11e821413478b903b5 (diff)
downloadcoreboot-274dabd7a04b18bc2f2378bb9faa7416dfd0ab83.tar.xz
src/northbridge: Remove unneeded include <arch/io.h>
Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/early_reset.c1
-rw-r--r--src/northbridge/intel/gm45/romstage.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index 3f095a256f..b5aa8044be 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -15,7 +15,6 @@
*/
#include <types.h>
-#include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 15d3c3a344..38f2d5f68f 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -18,7 +18,6 @@
#include <cbmem.h>
#include <romstage_handoff.h>
#include <console/console.h>
-#include <arch/io.h>
#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <cpu/x86/lapic.h>