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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-05 18:05:17 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-24 22:56:52 +0000 |
commit | e39becf5216419fa0a08c1d8632474fd8a9a5738 (patch) | |
tree | e4baed9dcf299738c09930d12421672b0133c478 /src/northbridge/intel/gm45 | |
parent | c00e2fb9966a9c4bd30944a198ad036ee81a2b0d (diff) | |
download | coreboot-e39becf5216419fa0a08c1d8632474fd8a9a5738.tar.xz |
intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.
Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r-- | src/northbridge/intel/gm45/Kconfig | 1 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/Makefile.inc | 2 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index dda52dddf2..3042741370 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_GM45 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select LAPIC_MONOTONIC_TIMER select VGA select INTEL_EDID select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 0ab1c94a27..3742cfcf7c 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -35,8 +35,6 @@ ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c -smm-y += ../../../cpu/x86/lapic/apic_timer.c - postcar-y += memmap.c endif |