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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-07-08 12:39:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-09 09:29:53 +0000 |
| commit | fd051dc018346e5947d9d8733e269fc5020236ba (patch) | |
| tree | d12a70629b7565c20643c97ca8a933c4344e5b7b /src/northbridge/intel/gm45 | |
| parent | 95bca33efa280e606f7c6d41541cec67c0eb227f (diff) | |
| download | coreboot-fd051dc018346e5947d9d8733e269fc5020236ba.tar.xz | |
src/northbridge: Use "foo *bar" instead of "foo* bar"
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/iommu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 77aba94b4a..0108116666 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -54,7 +54,7 @@ void init_iommu() u8 cmd = pci_read_config8(igd, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(igd, PCI_COMMAND, cmd); - void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0); + void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); /* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20); |