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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-12 11:54:08 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-06-12 11:46:18 +0200 |
| commit | 049347fee0e25c87c3f60b125ee5e03109429fb0 (patch) | |
| tree | 0a3c69cef4722e22b485bd8002d8cd141b683b35 /src/northbridge/intel/gm45 | |
| parent | 9ed74b54b573d9f26ccd1ec382206c5c0c8048ff (diff) | |
| download | coreboot-049347fee0e25c87c3f60b125ee5e03109429fb0.tar.xz | |
nb/intel/gm45: Add romstage timestamps
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 30e9297a06..d2da3b02ab 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <lib.h> #include <delay.h> +#include <timestamp.h> #include "gm45.h" #include "chip.h" @@ -1713,6 +1714,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) int ch; u8 reg8; + timestamp_add_now(TS_BEFORE_INITRAM); /* Wait for some bit, maybe TXT clear. */ if (sysinfo->txt_enabled) { @@ -1825,4 +1827,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) raminit_thermal(sysinfo); init_igd(sysinfo); + + timestamp_add_now(TS_AFTER_INITRAM); } |