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authorArthur Heymans <arthur@aheymans.xyz>2018-01-25 21:38:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:45:34 +0000
commit6336d4c48d2f85629ff668da36711ea794f70ab5 (patch)
tree1cafe0dde00967c76897312d80fca723bf0a2f79 /src/northbridge/intel/gm45
parentea415b335f57bde8e744e0f40845cc6fdd671c71 (diff)
downloadcoreboot-6336d4c48d2f85629ff668da36711ea794f70ab5.tar.xz
nb/intel/gm45: Use parallel MP init
This places the parallel mp ops up in the model_1067x dir and is included from other Intel core2 CPU dirs that can use the same code. Tested on Thinkpad X200 on which boot time is reduced by ~35ms. Change-Id: Iac416f671407246ee223075eee1aff511e612889 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/23434 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/Kconfig1
-rw-r--r--src/northbridge/intel/gm45/northbridge.c22
2 files changed, 2 insertions, 21 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index e7b96037dd..ef6b4ef582 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select SMM_TSEG
+ select PARALLEL_MP
config CBFS_SIZE
hex
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 7ff046e9f3..791559b518 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -230,26 +230,6 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(dev, D0F0_SMRAM, smram);
}
-/*
- * Really doesn't belong here but will go away with parallel mp init,
- * so let it be here for a while...
- */
-int cpu_get_apic_id_map(int *apic_id_map)
-{
- unsigned int i;
-
- /* Logical processors (threads) per core */
- const struct cpuid_result cpuid1 = cpuid(1);
- /* Read number of cores. */
- const char cores = (cpuid1.ebx >> 16) & 0xf;
-
- /* TODO in parallel MP cpuid(1).ebx */
- for (i = 0; i < cores; i++)
- apic_id_map[i] = i;
-
- return cores;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
@@ -264,7 +244,7 @@ static struct device_operations pci_domain_ops = {
static void cpu_bus_init(struct device *dev)
{
- initialize_cpus(dev->link_list);
+ bsp_init_and_start_aps(dev->link_list);
}
static struct device_operations cpu_bus_ops = {