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author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-18 22:49:36 +0100 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-20 20:27:51 +0000 |
commit | a1e22b8192d5fc85995a41d0961c25293ba4391f (patch) | |
tree | 7b7dbc885d3ac99fe029cf0961eda1052e753dc1 /src/northbridge/intel/gm45 | |
parent | 0eb4db185cfef44ddfdbd91d4fe69a48c127fa84 (diff) | |
download | coreboot-a1e22b8192d5fc85995a41d0961c25293ba4391f.tar.xz |
src: Use 'include <string.h>' when appropriate
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r-- | src/northbridge/intel/gm45/acpi.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/pm.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/romstage.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/thermal.c | 3 |
6 files changed, 4 insertions, 6 deletions
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 301743ce4a..decf712302 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -15,13 +15,13 @@ */ #include <types.h> -#include <string.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> + #include "gm45.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 40e4f61afd..f011cce8d7 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -20,11 +20,11 @@ #include <device/device.h> #include <device/pci.h> #include <stdlib.h> -#include <string.h> #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> #include <cpu/intel/smm/gen1/smi.h> + #include "chip.h" #include "gm45.h" diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index c470b8147c..4199274f3c 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <stddef.h> -#include <string.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index a447a23093..d96bcf4528 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <stddef.h> -#include <string.h> #include <device/pci_def.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 7335ac914f..09439f25ef 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -27,6 +27,7 @@ #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/gpio.h> +#include <string.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 3ed75b30af..1629a67b8d 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -16,11 +16,10 @@ #include <stdint.h> #include <stddef.h> -#include <string.h> #include <device/pci_def.h> #include <spd.h> -#include "delay.h" +#include "delay.h" #include "gm45.h" void raminit_thermal(const sysinfo_t *sysinfo) |