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author | Nico Huber <nico.h@gmx.de> | 2020-04-26 19:26:36 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2020-05-27 21:35:06 +0000 |
commit | dfdf102000584e38952122c74858e46fa69acc60 (patch) | |
tree | e4b6b08d5a2a6096d51118ed7879bce1b45653e5 /src/northbridge/intel/gm45 | |
parent | 826094f65cf8778bd120e08917ef5557d0bad49d (diff) | |
download | coreboot-dfdf102000584e38952122c74858e46fa69acc60.tar.xz |
intel/gma: Don't bluntly enable I/O
The allocator should take care of this.
Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r-- | src/northbridge/intel/gm45/gma.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index e9bd722da9..b48b3c3100 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -154,7 +154,7 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |