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| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-12-27 14:18:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-31 15:22:43 +0000 |
| commit | 4a216475f5382d4b0ccf5fb65cd79b7ca3b32ed4 (patch) | |
| tree | 967e60522f0b58aa8cbbb382c596d3f0b3bd4f7d /src/northbridge/intel/gm45 | |
| parent | d225834220cfbe59850a97092674c4d55faff757 (diff) | |
| download | coreboot-4a216475f5382d4b0ccf5fb65cd79b7ca3b32ed4.tar.xz | |
src: Remove some romcc workarounds
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel/gm45')
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index dda2b585f1..58b99ac40b 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -14,9 +14,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> -/* Just re-define these instead of including gm45.h. It blows up romcc. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 +#include "gm45.h" void bootblock_early_northbridge_init(void) { |