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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-28 20:27:31 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-06 16:11:45 +0000 |
| commit | 485c0ad0783aa168feab8944e498a393774512fd (patch) | |
| tree | 9e0d363d5f54b78b23f2def3097ee49da2f8f277 /src/northbridge/intel/haswell/Makefile.inc | |
| parent | 921fa84f9e6802b28dd42cb905c396d033e64836 (diff) | |
| download | coreboot-485c0ad0783aa168feab8944e498a393774512fd.tar.xz | |
inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
Tested to display the register content correctly on a Lenovo Thinkpad
X220.
Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/haswell/Makefile.inc')
0 files changed, 0 insertions, 0 deletions