diff options
author | Chris Morgan <macromorgan@hotmail.com> | 2020-02-07 09:40:42 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 07:54:26 +0000 |
commit | 5e5e789f9b115f7fb1e7c453cdf20df088ac893d (patch) | |
tree | 0b4a2bd0c1658ed770485947b468073450345ae0 /src/northbridge/intel/haswell/acpi | |
parent | efc4be6bf1b132f8d280b7b840049ea6677405d3 (diff) | |
download | coreboot-5e5e789f9b115f7fb1e7c453cdf20df088ac893d.tar.xz |
nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the
Haswell northbridge. This code is necessary to support the dGPU of the
t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated
to the correct Haswell values. Tested on t440p with dGPU on Ubuntu
18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is
unable to read the VBIOS of the dGPU as it has an invalid checksum (I
checked that the ROM in CBFS is correct). With this patch DRM works
correctly with both the Nouveau driver and the Nvidia proprietary
driver. Windows 10 1909 also tested but generates bluescreen once GPU
driver is loaded.
Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/haswell/acpi')
-rw-r--r-- | src/northbridge/intel/haswell/acpi/haswell.asl | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 3 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/acpi/peg.asl | 60 |
3 files changed, 63 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 45ebff29f1..2db72d7842 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -16,6 +16,7 @@ #include "../haswell.h" #include "hostbridge.asl" +#include "peg.asl" #include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 19d788ce26..d567701cb7 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -36,7 +36,8 @@ Device (MCHC) MHEN, 1, // Enable , 13, // MHBR, 22, // MCHBAR - + Offset (0x54), + DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl new file mode 100644 index 0000000000..c4af375422 --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/peg.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + Method (_STA) + { + Return (((\_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG1) +{ + Name (_ADR, 0x00010001) + + Method (_STA) + { + Return (((\_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} + +Device (PEG2) +{ + Name (_ADR, 0x00010002) + + Method (_STA) + { + Return (((\_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) + } + + Device (DEV0) + { + Name(_ADR, 0x00000000) + } +} |