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author | Tristan Corrick <tristan@corrick.kiwi> | 2018-10-31 02:27:29 +1300 |
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committer | Nico Huber <nico.h@gmx.de> | 2018-11-01 22:23:52 +0000 |
commit | 1a73eb08e79b4a53702ff9e9103bb3352391892b (patch) | |
tree | db1a824ac9abb5ee78f96bda5dabc7dd2d3dc2f1 /src/northbridge/intel/haswell/chip.h | |
parent | fdf907e4405e5df84e9d5a29735e0506782d9c6d (diff) | |
download | coreboot-1a73eb08e79b4a53702ff9e9103bb3352391892b.tar.xz |
nb/intel/haswell/gma: Support boards that have DDI E connected
On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.
Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.
[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
Volume 2c: Command Reference: Registers (Haswell)
https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family
Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/chip.h')
-rw-r--r-- | src/northbridge/intel/haswell/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 098bc335f9..fdabc3fc9a 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -40,6 +40,8 @@ struct northbridge_intel_haswell_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + bool gpu_ddi_e_connected; + struct i915_gpu_controller_info gfx; }; |