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| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-15 00:49:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:54:00 +0000 |
| commit | 1db5bc7dac2bb592708f26dede339ffdf3246567 (patch) | |
| tree | d8636a114ebd6ef6830a016de15c92b21f0b740d /src/northbridge/intel/haswell/finalize.c | |
| parent | 3663d55a23fb64ea88dd1fd18ae4b0ce29e71a61 (diff) | |
| download | coreboot-1db5bc7dac2bb592708f26dede339ffdf3246567.tar.xz | |
nb/intel/haswell: Tidy up code and comments
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/finalize.c')
| -rw-r--r-- | src/northbridge/intel/haswell/finalize.c | 46 |
1 files changed, 22 insertions, 24 deletions
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index ca36634f36..024d44e728 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -17,35 +17,33 @@ #include <device/pci_ops.h> #include "haswell.h" -#define PCI_DEV_HSW PCI_DEV(0, 0, 0) - void intel_northbridge_haswell_finalize_smm(void) { - pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0); /* GGC */ - pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10); /* ME */ - pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(HOST_BRIDGE, 0x50, 1 << 0); /* GGC */ + pci_or_config32(HOST_BRIDGE, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(HOST_BRIDGE, 0x78, 1 << 10); /* ME */ + pci_or_config32(HOST_BRIDGE, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(HOST_BRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(HOST_BRIDGE, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(HOST_BRIDGE, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(HOST_BRIDGE, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(HOST_BRIDGE, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1UL << 31); - MCHBAR32_OR(0x7000, 1UL << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; + MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); } |