diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-01-17 09:39:39 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-18 17:11:24 +0100 |
| commit | 21efd8c0378a8a42ee2fd71957be318416b6f5af (patch) | |
| tree | 2a130f741bd22afa3e7a2748049f6890cd9a1037 /src/northbridge/intel/haswell/haswell.h | |
| parent | 7af20698f69bbf10c4f18aa4fcc35ae7cf8cb866 (diff) | |
| download | coreboot-21efd8c0378a8a42ee2fd71957be318416b6f5af.tar.xz | |
haswell: fix ACPI MCFG table
The acpi_fill_mcfg() was still using ivy/sandy PCI device ids which Hawell
obviously doesn't have. This resulted in an empty MCFG table. Instead of
relying on PCI device ids use dev/fn 0/0 since that is where the host
bridge always resides. Additionally remove the defines for the IB and SB
pci device ids. Replace them with mobile and ult Haswel device ids and
use those in the pci driver tables for the northbridge code.
Booted to Linux and noted that MCFG was properly parsed.
Change-Id: Ieaab2dfef0e9daf3edbd8a27efe0825d2beb9443
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2748
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/haswell.h')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bbb51aaf81..3a1803858a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -204,8 +204,8 @@ struct ied_header { u8 reserved[34]; } __attribute__ ((packed)); -#define PCI_DEVICE_ID_SB 0x0104 -#define PCI_DEVICE_ID_IB 0x0154 +#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 +#define PCI_DEVICE_ID_HSW_ULT 0x0a04 #ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); |