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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-03 21:28:40 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-07 05:42:15 +0000 |
commit | fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 (patch) | |
tree | b0e0c39376de50d41f3d6e21ed4b3aa47262d897 /src/northbridge/intel/haswell/memmap.c | |
parent | e119d86ca87937d45e67d00da722c28ac7ceaa9e (diff) | |
download | coreboot-fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886.tar.xz |
northbridge/intel: Rename ram_calc.c to memmap.c
Use a name consistent with the more recent soc/intel.
Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/haswell/memmap.c')
-rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c new file mode 100644 index 0000000000..3a63afcde6 --- /dev/null +++ b/src/northbridge/intel/haswell/memmap.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <device/pci_ops.h> +#include <cbmem.h> +#include <stage_cache.h> +#include "haswell.h" + +static uintptr_t smm_region_start(void) +{ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignment. + */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} |