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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-10-15 17:19:41 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-01-15 15:29:52 +0100 |
commit | cb08e169cf959333206ef69d8aa82808ef797eb7 (patch) | |
tree | f025f6d243e815821ae70d8febbdb415025d7dfa /src/northbridge/intel/haswell/ram_calc.c | |
parent | bbf013c38fe76cf9cc107c41c17e4ac432847d28 (diff) | |
download | coreboot-cb08e169cf959333206ef69d8aa82808ef797eb7.tar.xz |
CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.
Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.
Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell/ram_calc.c')
-rw-r--r-- | src/northbridge/intel/haswell/ram_calc.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c new file mode 100644 index 0000000000..99e7d672b9 --- /dev/null +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "haswell.h" + +unsigned long get_top_of_ram(void) +{ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignement. + */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom & ~((1 << 20) - 1); +} |