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| author | Aaron Durbin <adurbin@chromium.org> | 2012-12-07 09:50:40 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 05:10:00 +0100 |
| commit | b6b5aa15cecf2a9226bf5c265f15bf905c90e558 (patch) | |
| tree | 517cf7791a5bec1b0012288a17ea46d045ebfa7b /src/northbridge/intel/haswell/raminit.c | |
| parent | 68724fd1e327d3e33c93bceec56973c0a4f7f505 (diff) | |
| download | coreboot-b6b5aa15cecf2a9226bf5c265f15bf905c90e558.tar.xz | |
haswell: Remove logic to send dram init done to ME
The reference code sends the dram init done command to the ME.
Therefore, there is no need for coreboot to do this.
Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2633
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/raminit.c')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 09c8fc4d78..0c68e60707 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -216,13 +216,7 @@ void sdram_initialize(struct pei_data *pei_data) version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); - /* Send ME init done for SandyBridge here. This is done - * inside the SystemAgent binary on IvyBridge. */ - if (BASE_REV_SNB == - (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); - else - intel_early_me_status(); + intel_early_me_status(); report_memory_config(); |