diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 12:06:04 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:16:58 +0000 |
commit | 2e25ac6afe84d9535fa6d89b847915e96f5d266b (patch) | |
tree | 3c05edec71d4e1215d864eccb61a9ae0a0b7717e /src/northbridge/intel/haswell/romstage.c | |
parent | 284a54775bf17f5192b164a4b9d09a06fcd747cd (diff) | |
download | coreboot-2e25ac6afe84d9535fa6d89b847915e96f5d266b.tar.xz |
haswell: relocate `romstage_common` to northbridge
Other platforms do this as well. It will ease refactoring on follow-ups.
Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel/haswell/romstage.c')
-rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c new file mode 100644 index 0000000000..579eca791b --- /dev/null +++ b/src/northbridge/intel/haswell/romstage.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cf9_reset.h> +#include <timestamp.h> +#include <cpu/x86/lapic.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <romstage_handoff.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> + +void romstage_common(const struct romstage_params *params) +{ + int wake_from_s3; + + enable_lapic(); + + wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + haswell_early_initialization(); + printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); + + if (wake_from_s3) { +#if CONFIG(HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + wake_from_s3 = 0; +#endif + } + + /* Prepare USB controller early in S3 resume */ + if (wake_from_s3) + enable_usb_bar(); + + post_code(0x3a); + + /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ + params->pei_data->boot_mode = wake_from_s3 ? 2 : 0; + + timestamp_add_now(TS_BEFORE_INITRAM); + + report_platform_info(); + + if (params->copy_spd != NULL) + params->copy_spd(params->pei_data); + + sdram_initialize(params->pei_data); + + timestamp_add_now(TS_AFTER_INITRAM); + + post_code(0x3b); + + intel_early_me_status(); + + if (!wake_from_s3) { + cbmem_initialize_empty(); + /* Save data returned from MRC on non-S3 resumes. */ + save_mrc_data(params->pei_data); + } else if (cbmem_initialize()) { + #if CONFIG(HAVE_ACPI_RESUME) + /* Failed S3 resume, reset to come up cleanly */ + system_reset(); + #endif + } + + haswell_unhide_peg(); + + setup_sdram_meminfo(params->pei_data); + + romstage_handoff_init(wake_from_s3); + + post_code(0x3f); +} |