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author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 12:29:03 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-11 20:49:25 +0000 |
commit | 73fa035b2053870776c9c81a821b6a1603dc13f1 (patch) | |
tree | 8cd4215b0bdcfd13146de90c43af2533a363acb7 /src/northbridge/intel/haswell/romstage.c | |
parent | c06648b8c1f33e0f9d2356edc740e7661b7eb4f2 (diff) | |
download | coreboot-73fa035b2053870776c9c81a821b6a1603dc13f1.tar.xz |
nb/intel/haswell: Add `mb_late_romstage_setup` function
This function is called at the end of `romstage_common`. Only one board
makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call
it after `romstage_common` has done nearly everything.
Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/romstage.c')
-rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 8cf2e7ca71..ae9d707d90 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -13,6 +13,10 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/me.h> +void __weak mb_late_romstage_setup(void) +{ +} + void romstage_common(const struct romstage_params *params) { int wake_from_s3; @@ -77,5 +81,7 @@ void romstage_common(const struct romstage_params *params) romstage_handoff_init(wake_from_s3); + mb_late_romstage_setup(); + post_code(0x3f); } |