diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-02-13 10:30:42 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-16 20:42:41 +0100 |
| commit | 6a360048a1a4f8eaebbf9c4ec75fe4a9543421b2 (patch) | |
| tree | 7a8aac4c6a25c6a5a69d174a51faf8afc9824fdc /src/northbridge/intel/haswell | |
| parent | b4b9eb399ef2f5539afce6e43b49d4cf1613ae9e (diff) | |
| download | coreboot-6a360048a1a4f8eaebbf9c4ec75fe4a9543421b2.tar.xz | |
haswell: backup the default SMM region on resume
Haswell CPUs need to use the default SMM region for
relocating to the desired SMM location. Back up that
memory on resume instead of reserving the default
region. This makes the haswell support more forgiving
to software which expects PC-compatible memory layouts.
Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5217
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8d57c03b16..010cc07104 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -305,10 +305,7 @@ static void mc_add_dram_resources(device_t dev) /* * These are the host memory ranges that should be added: - * - 0 -> SMM_DEFAULT_BASE : cacheable - * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : - * cacheable and reserved - * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable + * - 0 -> 0xa0000: cacheable * - 0xc0000 -> TSEG : cacheable * - TESG -> BGSM: cacheable with standard MTRRs and reserved * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved @@ -338,21 +335,8 @@ static void mc_add_dram_resources(device_t dev) */ index = 0; - /* 0 - > SMM_DEFAULT_BASE */ + /* 0 - > 0xa0000 */ base_k = 0; - size_k = SMM_DEFAULT_BASE >> 10; - ram_resource(dev, index++, base_k, size_k); - - /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */ - resource = new_resource(dev, index++); - resource->base = SMM_DEFAULT_BASE; - resource->size = SMM_DEFAULT_SIZE; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_CACHEABLE | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ - base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); |