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authorAngel Pons <th3fanbus@gmail.com>2020-07-04 01:24:59 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-12 11:16:12 +0000
commit8aab7876d186ed9a8e978ec06a83a46f74a6179b (patch)
tree5069b7aa81401f9606021cc8e25f9d52192f7ea7 /src/northbridge/intel/haswell
parent39a6093d7937dec85077f754fbcaa2e2be493eae (diff)
downloadcoreboot-8aab7876d186ed9a8e978ec06a83a46f74a6179b.tar.xz
haswell: Move some MRC settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
-rw-r--r--src/northbridge/intel/haswell/chip.h6
-rw-r--r--src/northbridge/intel/haswell/romstage.c6
2 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 593144d1d0..28c082838d 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -32,6 +32,12 @@ struct northbridge_intel_haswell_config {
bool gpu_ddi_e_connected;
+ bool ec_present;
+
+ bool dq_pins_interleaved;
+
+ bool usb_xhci_on_resume;
+
struct i915_gpu_controller_info gfx;
};
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 7016fd9a7e..dfadad24aa 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -10,6 +10,7 @@
#include <commonlib/helpers.h>
#include <romstage_handoff.h>
#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/chip.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -40,6 +41,8 @@ void mainboard_romstage_entry(void)
{
const struct device *gbe = pcidev_on_root(0x19, 0);
+ const struct northbridge_intel_haswell_config *cfg = config_of_soc();
+
int wake_from_s3;
struct pei_data pei_data = {
@@ -56,9 +59,12 @@ void mainboard_romstage_entry(void)
.temp_mmio_base = 0xfed08000,
.system_type = get_pch_platform_type(),
.tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .ec_present = cfg->ec_present,
.gbe_enable = gbe && gbe->enabled,
.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
+ .dq_pins_interleaved = cfg->dq_pins_interleaved,
.max_ddr3_freq = 1600,
+ .usb_xhci_on_resume = cfg->usb_xhci_on_resume,
};
mainboard_fill_pei_data(&pei_data);