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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-01 13:43:02 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-01 20:32:15 +0000 |
commit | f1b58b78351d7ed220673e688a2f7bc9e96da4e2 (patch) | |
tree | d8aae223f0e426f189cb4750b972a31e09d46b88 /src/northbridge/intel/haswell | |
parent | 44e89af6e609874f2f18d30f1e66dce8b5a98eff (diff) | |
download | coreboot-f1b58b78351d7ed220673e688a2f7bc9e96da4e2.tar.xz |
device/pci: Fix PCI accessor headers
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/haswell')
-rw-r--r-- | src/northbridge/intel/haswell/acpi.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/bootblock.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/gma.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/ram_calc.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/haswell/report_platform.c | 1 |
5 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index f655c3b6fb..d92e858d53 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -20,6 +20,7 @@ #include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "haswell.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index a25f363177..d7f4e6e9e9 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> /* Just re-define this instead of including haswell.h. It blows up romcc. */ #define PCIEXBAR 0x60 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index be83894f33..a04b3f4720 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> #include <bootmode.h> diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index d3e88f2f84..24fbb64b97 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 1bc31108f5..376e63f7d5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -18,6 +18,7 @@ #include <string.h> #include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cpu/x86/msr.h> #include "haswell.h" |