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authorDuncan Laurie <dlaurie@chromium.org>2013-06-03 10:41:12 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-02 21:53:51 +0100
commitbcfcfa4473357eb6272bc8bcc5e03f4ba517bcd2 (patch)
tree1d08cb4bc9e40f38d8528b2f31630c9db7bda423 /src/northbridge/intel/haswell
parenta6c29fe6841ad5e03ddb35803943bed3bc83dfd2 (diff)
downloadcoreboot-bcfcfa4473357eb6272bc8bcc5e03f4ba517bcd2.tar.xz
haswell: Update pei_data to match ref code
- Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4219 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
-rw-r--r--src/northbridge/intel/haswell/pei_data.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index 73118290bd..b7dc8cf57a 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -31,16 +31,31 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 12
+#define PEI_VERSION 13
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
#define USB_OC_PIN_SKIP 8
+enum usb2_port_location {
+ USB_PORT_BACK_PANEL = 0,
+ USB_PORT_FRONT_PANEL,
+ USB_PORT_DOCK,
+ USB_PORT_MINI_PCIE,
+ USB_PORT_FLEX,
+ USB_PORT_INTERNAL,
+ USB_PORT_SKIP
+};
+
+/* Usb Port Length:
+ * [16:4] = length in inches in octal format
+ * [3:0] = decimal point
+ */
struct usb2_port_setting {
uint16_t length;
uint8_t enable;
uint8_t over_current_pin;
+ uint8_t location;
} __attribute__((packed));
struct usb3_port_setting {
@@ -75,6 +90,8 @@ struct pei_data
// 3 = disable dimm 0+1 on channel
int dimm_channel0_disabled;
int dimm_channel1_disabled;
+ /* Enable 2x Refresh Mode */
+ int ddr_refresh_2x;
/* Data read from flash and passed into MRC */
unsigned char *mrc_input;
unsigned int mrc_input_len;