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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-04 19:34:59 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 10:01:35 +0000 |
| commit | faa5f9869d67ab1a963e1c49afaaf353503586c9 (patch) | |
| tree | a489e11b9225a4e93fefc42419095ce03f3eaee5 /src/northbridge/intel/haswell | |
| parent | 5e2ac2c0795628ab086da76304cd97b16e1d169f (diff) | |
| download | coreboot-faa5f9869d67ab1a963e1c49afaaf353503586c9.tar.xz | |
cpu/intel/haswell: Use the common intel romstage_main function
Tested on Google peppy (Acer C720).
Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/Kconfig | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index ae6d81285d..f9c68f34dd 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -58,13 +58,6 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. -config DCACHE_RAM_ROMSTAGE_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage from the data cache - during pre-ram ROM stage execution. - config HAVE_MRC bool "Add a System Agent binary" help |