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| author | Aaron Durbin <adurbin@chromium.org> | 2013-04-24 17:31:49 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-05-01 07:11:22 +0200 |
| commit | 243aa44b74935cfc969106dbbe2420ee4a2c39b2 (patch) | |
| tree | 645ee8f1e41ad05d2e29d786c86454bf406f82fa /src/northbridge/intel/haswell | |
| parent | 40131cfa46bc195ad3bdf2ce9b9af67dcbfd71ca (diff) | |
| download | coreboot-243aa44b74935cfc969106dbbe2420ee4a2c39b2.tar.xz | |
boot: remove cbmem_post_handling()
The cbmem_post_handling() function was implemented by 2
chipsets in order to save memory configuration in flash. Convert
both of these chipsets to use the boot state machine callbacks
to perform the saving of the memory configuration.
Change-Id: I697e5c946281b85a71d8533437802d7913135af3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/mrccache.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 5 |
3 files changed, 7 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index ba88722452..96438adec8 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -237,8 +237,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); #if !defined(__PRE_RAM__) -void update_mrc_cache(void); - #include "gma.h" int init_igd_opregion(igd_opregion_t *igd_opregion); #endif diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 032bae4131..f60d0f7993 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <ip_checksum.h> @@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -void update_mrc_cache(void) +static void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); @@ -222,6 +223,11 @@ void update_mrc_cache(void) flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); } + +BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { + BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + update_mrc_cache, NULL), +}; #endif struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 16196ad6ad..5c1ab3e1ff 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -53,11 +53,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; |