diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/northbridge/intel/haswell | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/haswell.asl | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index e9d35207c7..0f0d38339e 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 3b043a3b96..0fd0228268 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -35,7 +35,7 @@ #include "chip.h" #include "haswell.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -240,7 +240,7 @@ static void power_well_enable(void) * after we power up the AUX channel until we can talk to it. * So get that going right now. We can't turn on the panel, yet, just VDD. */ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); } } @@ -475,7 +475,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ac0b84f1d0..ad4563bb35 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -395,7 +395,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |