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| author | Nico Huber <nico.h@gmx.de> | 2020-04-26 17:01:25 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-05-27 21:34:49 +0000 |
| commit | f2a0be235cdf72caff549a1cfe0b986bdd99e93b (patch) | |
| tree | d2e66798375f6b644c97206d65684b9f7e95ce9d /src/northbridge/intel/haswell | |
| parent | 4dc4cb6b5c835ca947356a4d4e8c10228966bebc (diff) | |
| download | coreboot-f2a0be235cdf72caff549a1cfe0b986bdd99e93b.tar.xz | |
drivers/intel/gma: Move IGD OpRegion to CBMEM
It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.
TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
intel_backlight + acpi_video synchronize, both before and
after suspend.
Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 44 |
1 files changed, 2 insertions, 42 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0caa64fe11..ae9e25704d 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -4,7 +4,6 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <cbmem.h> #include <console/console.h> #include <bootmode.h> #include <delay.h> @@ -16,7 +15,6 @@ #include <drivers/intel/gma/libgfxinit.h> #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> -#include <southbridge/intel/lynxpoint/nvs.h> #include <string.h> #include <types.h> @@ -209,19 +207,6 @@ int gtt_poll(u32 reg, u32 mask, u32 value) return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); @@ -475,6 +460,8 @@ static void gma_func0_init(struct device *dev) int lightup_ok = 0; u32 reg32; + intel_gma_init_igd_opregion(); + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; @@ -509,7 +496,6 @@ static void gma_func0_init(struct device *dev) gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); } static void gma_generate_ssdt(const struct device *dev) @@ -519,31 +505,6 @@ static void gma_generate_ssdt(const struct device *dev) drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -555,7 +516,6 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { |