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author | Ed Swierk <eswierk@arastra.com> | 2008-03-16 23:36:00 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-03-16 23:36:00 +0000 |
commit | a9faea8977cae2c1c55b83b214aee6845de1c885 (patch) | |
tree | 3d8545f7fd12062a8177fd7f705f290b2d2c3e7f /src/northbridge/intel/i3100/memory_initialized.c | |
parent | aaea11b749ccd481a37424c38625873c231f850d (diff) | |
download | coreboot-a9faea8977cae2c1c55b83b214aee6845de1c885.tar.xz |
This patch implements support for the Intel 3100 integrated
northbridge and RAM controller.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i3100/memory_initialized.c')
-rw-r--r-- | src/northbridge/intel/i3100/memory_initialized.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/northbridge/intel/i3100/memory_initialized.c b/src/northbridge/intel/i3100/memory_initialized.c new file mode 100644 index 0000000000..9de6cfcabf --- /dev/null +++ b/src/northbridge/intel/i3100/memory_initialized.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "i3100.h" +#define NB_DEV PCI_DEV(0, 0, 0) + +static inline int memory_initialized(void) +{ + u32 drc; + drc = pci_read_config32(NB_DEV, DRC); + return (drc & (1<<29)); +} |