diff options
author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/northbridge/intel/i3100/pciexp_porta.c | |
parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) | |
download | coreboot-264566c177dac98e67c2a4765fe08c5d8de10753.tar.xz |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i3100/pciexp_porta.c')
-rw-r--r-- | src/northbridge/intel/i3100/pciexp_porta.c | 85 |
1 files changed, 0 insertions, 85 deletions
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c deleted file mode 100644 index 3f4939cace..0000000000 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pciexp.h> -#include <arch/io.h> -#include "chip.h" -#include <reset.h> - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } - -} - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag = 1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA1, -}; |