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authorMyles Watson <mylesgw@gmail.com>2010-06-09 22:41:35 +0000
committerMyles Watson <mylesgw@gmail.com>2010-06-09 22:41:35 +0000
commit894a34715f41f7c819a593dc3ff8e3033ffaa9fe (patch)
tree12ed2a5e10c6f181caa4c1add2ee8239abf82bfe /src/northbridge/intel/i3100
parent6507b390467591928f16aab68f247321ad3f2262 (diff)
downloadcoreboot-894a34715f41f7c819a593dc3ff8e3033ffaa9fe.tar.xz
Same conversion as with resources from static arrays to lists, except
there is no free list. Converting resource arrays to lists reduced the size of each device struct from 1092 to 228 bytes. Converting link arrays to lists reduced the size of each device struct from 228 to 68 bytes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i3100')
-rw-r--r--src/northbridge/intel/i3100/northbridge.c8
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta_ep80579.c2
2 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 0675aea6bc..482e6006a5 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -83,7 +83,7 @@ static void pci_domain_set_resources(device_t dev)
device_t mc_dev;
u32 pci_tolm;
- pci_tolm = find_pci_tolm(&dev->link[0]);
+ pci_tolm = find_pci_tolm(dev->link_list);
#if 1
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
@@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev)
pci_tolm = 0xe0000000;
/* Ensure pci_tolm is 128M aligned */
pci_tolm &= 0xf8000000;
- mc_dev = dev->link[0].children;
+ mc_dev = dev->link_list->children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
* This is all computed in kilobytes and converted to/from
@@ -172,7 +172,7 @@ static void pci_domain_set_resources(device_t dev)
high_tables_size = HIGH_TABLES_SIZE * 1024;
#endif
}
- assign_resources(&dev->link[0]);
+ assign_resources(dev->link_list);
}
static u32 i3100_domain_scan_bus(device_t dev, u32 max)
@@ -240,7 +240,7 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
index 42f624aaf7..a17cb0b3f2 100644
--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -56,7 +56,7 @@ static void pcie_init(struct device *dev)
static void pcie_bus_enable_resources(struct device *dev)
{
- if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n");
pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8);