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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-08 01:53:24 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-11 08:39:07 +0200 |
| commit | 7116ac803736345cc7c7b73ac435efa50c4cd2b0 (patch) | |
| tree | 64b7190ef4e61ba2e17a88c50e92c076c3aa2d19 /src/northbridge/intel/i3100 | |
| parent | c805e62f9dd5e1b11906101845abd36b049e7dc3 (diff) | |
| download | coreboot-7116ac803736345cc7c7b73ac435efa50c4cd2b0.tar.xz | |
src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating
common helpers. This makes the code base more consistent and
unified/tight.
Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/i3100')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 90c1005b4c..962b7aa86b 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -335,7 +335,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH); val <<= 2; /* convert to 1/4 ns */ val += byte40rem[(val1 >> 4) & 0x7]; - val = (val + ci - 1) / ci + 1; /* convert to cycles */ + val = CEIL_DIV(val, ci) + 1; /* convert to cycles */ if (trc < val) trc = val; val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT); @@ -343,7 +343,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, if (val1 & 0x01) val += 1024; val += byte40rem[(val1 >> 1) & 0x7]; - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (trfc < val) trfc = val; } @@ -360,15 +360,15 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, continue; val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); val <<= 2; /* convert to 1/4 ns */ - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (tras < val) tras = val; val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY); - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (trtp < val) trtp = val; val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY); - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (twtr < val) twtr = val; } |