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| author | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-09 15:56:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-11 20:51:33 +0100 |
| commit | 8cc846897132f6d6baa49118005815aefb5f560f (patch) | |
| tree | 113b69cccb4728084be3c5f83f04fe9f56db43e5 /src/northbridge/intel/i3100 | |
| parent | 3b19cbae37ab340bd530e35412800a171733fda6 (diff) | |
| download | coreboot-8cc846897132f6d6baa49118005815aefb5f560f.tar.xz | |
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h
Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i3100')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 5 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index b453e8ba87..fa42efcac4 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -21,6 +21,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/intel/speedstep.h> #include <stdlib.h> #include "raminit.h" #include "i3100.h" @@ -583,7 +584,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (1 << 4); /* independent clocks */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ value = msr.lo & 0x07; drc &= ~(3 << 2); drc |= (fsb_conversion[value] << 2); diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5fe206ff2a..4c688d55e9 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -20,6 +20,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/intel/speedstep.h> #include "raminit_ep80579.h" #include "ep80579.h" @@ -441,8 +442,8 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, /* TODO check: */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ - print_debug("msr 0xcd = "); + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ + print_debug("MSR FSB_FREQ(0xcd) = "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); |