Drop \r\n and \n\r as both print_XXX and printk now do this internally.

Only some assembler files still have \r\n ... Can we move that part to C
completely?

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 77 insertions, 77 deletions

diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 76475ce235..fa44d599f1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -76,7 +76,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 }
 
 struct dimm_size {
@@ -149,7 +149,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	sz.side1 = 0;
@@ -277,7 +277,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	dra = 0;
@@ -528,7 +528,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 
 	}
 	else {
-		die("Invalid SPD 9 bus speed.\r\n");
+		die("Invalid SPD 9 bus speed.\n");
 	}
 
 	/* 0x78 DRT */
@@ -556,7 +556,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 			continue;
 		}
 		value = spd_read_byte(ctrl->channel0[cnt], 11);	/* ECC */
-		if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
+		if (value != 2) die("ERROR - Non ECC memory dimm\n");
 
 		value = spd_read_byte(ctrl->channel0[cnt], 12);	/*refresh rate*/
 		value &= 0x0f;    /* clip self refresh bit */
@@ -595,7 +595,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	drc = 0;
@@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	/* Test if we can read the spd and if ram is ddr or ddr2 */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -683,12 +683,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 		data32 = 0x777becdc; /* ESSD */
 		break;
 	    }
-	    die("Error - First dimm slot empty\r\n");
+	    die("Error - First dimm slot empty\n");
 	}
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
   	pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 
@@ -921,7 +921,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 	print_debug_hex32(recena);
 	print_debug(",  Receive enable B = ");
 	print_debug_hex32(recenb);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* clear out the calibration area */
 	write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -977,7 +977,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		0xffffffff, 0xffffffff, 0x000000ff};
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* 0x80 */
 #ifdef DIMM_MAP_LOGICAL
@@ -989,7 +989,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if( drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
 	data32 = data32 & ~(7 << 8);  /* clear refresh rates */
@@ -1024,7 +1024,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for(i=0;i<8;i+=2) { /* loop through each dimm to test */
 		print_debug("DIMM ");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		/* Apply NOP */
 		do_delay();
 
@@ -1177,7 +1177,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	write32(MCBAR+DCALCSR, 0x0008000f);
 
 	/* clear memory and init ECC */
-	print_debug("Clearing memory\r\n");
+	print_debug("Clearing memory\n");
 	for(i=0;i<64;i+=4) {
 		write32(MCBAR+DCALDATA+i, 0x00000000);
 	}
@@ -1194,13 +1194,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	data32 |= (1 << 31);
 	pci_write_config32(ctrl->f0, 0x98, data32);
 	/* wait for completion */
-	print_debug("Waiting for mem complete\r\n");
+	print_debug("Waiting for mem complete\n");
 	while(1) {
 		data32 = pci_read_config32(ctrl->f0, 0x98);
 		if( (data32 & (1<<31)) == 0)
 			break;
 	}
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 
 	/* Set initialization complete */
 	/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 9ad778bf13..5a4a328e44 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	sz.side1 = 0;
@@ -134,7 +134,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
 	print_debug_hex8(sz.side1);
 	print_debug(".");
 	print_debug_hex8(sz.side2);
-	print_debug("\r\n");
+	print_debug("\n");
 	return sz;
 
 }
@@ -167,14 +167,14 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
 	}
 	print_debug("DRB = ");
 	print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
-	print_debug("\r\n");
+	print_debug("\n");
 
 	cum >>= 1;
 	/* set TOM top of memory */
 	pci_write_config16(ctrl->f0, TOM, cum);
 	print_debug("TOM = ");
 	print_debug_hex16(cum);
-	print_debug("\r\n");
+	print_debug("\n");
 	/* set TOLM top of low memory */
 	if (cum > 0x18) {
 		cum = 0x18;
@@ -183,7 +183,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
 	pci_write_config16(ctrl->f0, TOLM, cum);
 	print_debug("TOLM = ");
 	print_debug_hex16(cum);
-	print_debug("\r\n");
+	print_debug("\n");
 	return 0;
 }
 
@@ -202,7 +202,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl)
 			print_debug_hex8(device);
 			print_debug(" = ");
 			print_debug_hex8(byte);
-			print_debug("\r\n");
+			print_debug("\n");
 			if (byte == 8) {
 				dimm_mask |= (1 << i);
 			}
@@ -227,29 +227,29 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 		}
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);
-		if (value < 0) die("Bad SPD data\r\n");
-		if ((value & 0xf) == 0) die("Invalid # of rows\r\n");
+		if (value < 0) die("Bad SPD data\n");
+		if ((value & 0xf) == 0) die("Invalid # of rows\n");
 		dra |= (((value-13) & 0x7) << 23);
 		dra |= (((value-13) & 0x7) << 29);
 		reg += value & 0xf;
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);
-		if (value < 0) die("Bad SPD data\r\n");
-		if ((value & 0xf) == 0) die("Invalid # of columns\r\n");
+		if (value < 0) die("Bad SPD data\n");
+		if ((value & 0xf) == 0) die("Invalid # of columns\n");
 		dra |= (((value-10) & 0x7) << 20);
 		dra |= (((value-10) & 0x7) << 26);
 		reg += value & 0xf;
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);
-		if (value < 0) die("Bad SPD data\r\n");
-		if ((value & 0xff) == 0) die("Invalid # of banks\r\n");
+		if (value < 0) die("Bad SPD data\n");
+		if ((value & 0xff) == 0) die("Invalid # of banks\n");
 		reg += log2(value & 0xff);
 
 		print_debug("dimm ");
 		print_debug_hex8(i);
 		print_debug(" reg = ");
 		print_debug_hex8(reg);
-		print_debug("\r\n");
+		print_debug("\n");
 
 		/* set device density */
 		dra |= ((31-reg));
@@ -270,7 +270,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 		print_debug_hex8(i);
 		print_debug(" = ");
 		print_debug_hex32(dra);
-		print_debug("\r\n");
+		print_debug("\n");
 
 		pci_write_config32(ctrl->f0, DRA + (i*4), dra);
 	}
@@ -320,10 +320,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
 	else if (val & 0x40)
 		cl = 6;
 	else
-		die("CAS latency mismatch\r\n");
+		die("CAS latency mismatch\n");
 	print_debug("cl = ");
 	print_debug_hex8(cl);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	ci = cycle[index];
 
@@ -349,10 +349,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
 	}
 	print_debug("trc = ");
 	print_debug_hex8(trc);
-	print_debug("\r\n");
+	print_debug("\n");
 	print_debug("trfc = ");
 	print_debug_hex8(trfc);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* Tras, Trtp, Twtr in cycles */
 	for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -374,38 +374,38 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
 	}
 	print_debug("tras = ");
 	print_debug_hex8(tras);
-	print_debug("\r\n");
+	print_debug("\n");
 	print_debug("trtp = ");
 	print_debug_hex8(trtp);
-	print_debug("\r\n");
+	print_debug("\n");
 	print_debug("twtr = ");
 	print_debug_hex8(twtr);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
 	       | ((cl - 3) << 6) | ((cl - 3) << 3));
 	print_debug("drt0 = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f0, DRT0, val);
 
 	val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
 	       | (twtr << 15));
 	print_debug("drt1 = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f0, DRT1, val);
 
 	val = (magic[index]);
 	print_debug("magic = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
 
 	val = (mrs[index] | (cl << 20));
 	print_debug("mrs = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	return val;
 }
 
@@ -422,11 +422,11 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 		if (!(dimm_mask & (1 << i)))
 			continue;
 		if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
-			die("ERROR: Only 64-bit DIMMs supported\r\n");
+			die("ERROR: Only 64-bit DIMMs supported\n");
 		if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
-			die("ERROR: Only ECC DIMMs supported\r\n");
+			die("ERROR: Only ECC DIMMs supported\n");
 		if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
-			die("ERROR: Only x8 DIMMs supported\r\n");
+			die("ERROR: Only x8 DIMMs supported\n");
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 		if (value > cycle)
@@ -434,7 +434,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	}
 	print_debug("cycle = ");
 	print_debug_hex8(cycle);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	drc |= (1 << 20); /* enable ECC */
 	drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -446,42 +446,42 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	print_debug("msr 0xcd = ");
 	print_debug_hex32(msr.hi);
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* TODO check that this msr really indicates fsb speed! */
 	if (msr.lo & 0x07) {
-		print_info("533 MHz FSB\r\n");
+		print_info("533 MHz FSB\n");
 		if (cycle <= 0x25) {
 			drc |= 0x5;
-			print_info("400 MHz DDR\r\n");
+			print_info("400 MHz DDR\n");
 		} else if (cycle <= 0x30) {
 			drc |= 0x7;
-			print_info("333 MHz DDR\r\n");
+			print_info("333 MHz DDR\n");
 		} else if (cycle <= 0x3d) {
 			drc |= 0x4;
-			print_info("266 MHz DDR\r\n");
+			print_info("266 MHz DDR\n");
 		} else {
 			drc |= 0x2;
-			print_info("200 MHz DDR\r\n");
+			print_info("200 MHz DDR\n");
 		}
 	}
 	else {
-		print_info("400 MHz FSB\r\n");
+		print_info("400 MHz FSB\n");
 		if (cycle <= 0x30) {
 			drc |= 0x7;
-			print_info("333 MHz DDR\r\n");
+			print_info("333 MHz DDR\n");
 		} else if (cycle <= 0x3d) {
 			drc |= 0x0;
-			print_info("266 MHz DDR\r\n");
+			print_info("266 MHz DDR\n");
 		} else {
 			drc |= 0x2;
-			print_info("200 MHz DDR\r\n");
+			print_info("200 MHz DDR\n");
 		}
 	}
 
 	print_debug("DRC = ");
 	print_debug_hex32(drc);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	return drc;
 }
@@ -494,7 +494,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	/* Test if we can read the SPD */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -524,14 +524,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
   	pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 
 	for (i = 0; i < 2; i++) {
 		print_debug("ODT CS");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -547,14 +547,14 @@ static void dump_dcal_regs(void)
 	int i;
 	for (i = 0x0; i < 0x2a0; i += 4) {
 		if ((i % 16) == 0) {
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex16(i);
 			print_debug(": ");
 		}
 		print_debug_hex32(read32(BAR+i));
 		print_debug(" ");
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 
@@ -570,12 +570,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	u16 data16;
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* Set DRAM type and Front Side Bus frequency */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if (drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
 	data32 = data32 | (3 << 5);  /* temp turn off ODT */
@@ -600,7 +600,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("NOP CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		udelay(16);
 		write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
 		write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -614,7 +614,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("NOP CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); 
 		data32 = read32(BAR+DCALCSR);
 		while (data32 & 0x80000000)
@@ -626,7 +626,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("Precharge CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -639,7 +639,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("EMRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -651,7 +651,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("MRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -664,7 +664,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("Precharge CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -678,7 +678,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		for (cs = 0; cs < 2; cs++) {	
 			print_debug("Refresh CS");
 			print_debug_hex8(cs);
-			print_debug("\r\n");
+			print_debug("\n");
 			write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
 			data32 = read32(BAR+DCALCSR);
 			while (data32 & 0x80000000)
@@ -691,7 +691,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("MRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -704,7 +704,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("EMRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -728,7 +728,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	for (cs = 0; cs < 1; cs++) {
 		print_debug("receive enable calibration CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
 		while (data32 & 0x80000000)
@@ -755,17 +755,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 			continue;
 		print_debug("clear memory CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
 		data32 = read32(BAR+MBCSR);
 		while (data32 & 0x80000000)
 			data32 = read32(BAR+MBCSR);
 		if (data32 & 0x40000000)
-			print_debug("failed!\r\n");
+			print_debug("failed!\n");
 	}
 
 	/* Clear read/write FIFO pointers */
-	print_debug("clear read/write fifo pointers\r\n");
+	print_debug("clear read/write fifo pointers\n");
 	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
 	udelay(16);
 	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -773,7 +773,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	dump_dcal_regs();
 
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 
 	/* Set initialization complete */
 	drc |= (1 << 29);