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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-27 19:37:31 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 04:40:27 +0200 |
| commit | 0f92f630556b4bf2e4c0696cae4c2f8e97eda334 (patch) | |
| tree | b97ad7a89a101c4770774035db5e4693043be928 /src/northbridge/intel/i440lx | |
| parent | 081651b6677c64a5f2861d831822b5f8f3517c21 (diff) | |
| download | coreboot-0f92f630556b4bf2e4c0696cae4c2f8e97eda334.tar.xz | |
Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel/i440lx')
| -rw-r--r-- | src/northbridge/intel/i440lx/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index 26c0c4bcb5..7d283a1941 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -416,7 +416,7 @@ static void sdram_enable(void) /* 0. Wait until power/voltages and clocks are stable (200us). */ udelay(200); - /* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */ + /* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 MHz). */ PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); |