Some more DIMM0 related cleanups and deduplication.

 - VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 10 insertions, 15 deletions

diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 44ee197284..16a908993a 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -7,7 +7,7 @@ void dump_spd_registers(void)
 	print_debug("\n");
 	for(i = 0; i < DIMM_SOCKETS; i++) {
 		unsigned device;
-		device = DIMM_SPD_BASE + i;
+		device = DIMM0 + i;
 		if (device) {
 			int j;
 			print_debug("dimm: ");
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 83b21b1286..df2916e835 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -255,12 +255,12 @@ static void spd_set_dram_size(void)
 
 	for (i = 0; i < DIMM_SOCKETS; i++) {
 		/* First check if a DIMM is actually present. */
-		if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
+		if (smbus_read_byte(DIMM0 + i, 2) == 4) {
 			print_debug("Found DIMM in slot ");
 			print_debug_hex8(i);
 			print_debug("\n");
 
-			dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
+			dimm_size = smbus_read_byte(DIMM0 + i, 31);
 
 			/* WISHLIST: would be nice to display it as decimal? */
 			print_debug("DIMM is 0x");
@@ -293,7 +293,7 @@ static void spd_set_dram_size(void)
 
 			/* If the DIMM is dual-sided, the DRP value is +2 */
 			/* TODO: Figure out asymetrical configurations. */
-			if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
+			if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) ==
 			    0xff) {
 				print_debug("DIMM is dual-sided\n");
 				dimm_size += 2;
@@ -361,20 +361,18 @@ static void set_dram_buffer_strength(void)
 
 	/* Check first slot. */
 	d0.size = d0.ds = d0.ss = 0;
-	if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
-	    == SPD_MEMORY_TYPE_SDRAM) {
-		d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
-		d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
+	if (smbus_read_byte(DIMM0, SPD_MEMORY_TYPE) == SPD_MEMORY_TYPE_SDRAM) {
+		d0.size = smbus_read_byte(DIMM0, SPD_BANK_DENSITY);
+		d0.ds = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) > 1;
 		d0.ss = !d0.ds;
 	}
 
 	/* Check second slot. */
 	d1.size = d1.ds = d1.ss = 0;
-	if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
+	if (smbus_read_byte(DIMM0 + 1, SPD_MEMORY_TYPE)
 	    == SPD_MEMORY_TYPE_SDRAM) {
-		d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
-		d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
-					SPD_NUM_DIMM_BANKS) > 1;
+		d1.size = smbus_read_byte(DIMM0 + 1, SPD_BANK_DENSITY);
+		d1.ds = smbus_read_byte(DIMM0 + 1, SPD_NUM_DIMM_BANKS) > 1;
 		d1.ss = !d1.ds;
 	}
 
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index fbf64239b2..186589a759 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -24,9 +24,6 @@
 /* The 82810 supports max. 2 dual-sided DIMMs. */
 #define DIMM_SOCKETS	2
 
-/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
-#define DIMM_SPD_BASE 0x50
-
 /* Function prototypes. */
 void sdram_set_registers(void);
 void sdram_set_spd_registers(void);