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| author | Martin Roth <martinroth@google.com> | 2016-11-18 09:29:03 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-21 23:43:54 +0100 |
| commit | 128c104c4d3b91d3371b03840af460d776af819d (patch) | |
| tree | bb0621ae2c90b512948ba9fee350cf42a49f4db3 /src/northbridge/intel/i82830/raminit.c | |
| parent | c6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4 (diff) | |
| download | coreboot-128c104c4d3b91d3371b03840af460d776af819d.tar.xz | |
nb/intel: Fix some spelling mistakes in comments and strings
Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17478
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/i82830/raminit.c')
| -rw-r--r-- | src/northbridge/intel/i82830/raminit.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c index bd92ac1fe8..7850c8749a 100644 --- a/src/northbridge/intel/i82830/raminit.c +++ b/src/northbridge/intel/i82830/raminit.c @@ -159,7 +159,7 @@ static void initialize_dimm_rows(void) } /*----------------------------------------------------------------------------- -DIMM-independant configuration functions. +DIMM-independent configuration functions. -----------------------------------------------------------------------------*/ struct dimm_size { @@ -206,7 +206,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) } /* SPD byte 31 is the memory size divided by 4 so we - * need to muliply by 4 to get the total size. + * need to multiply by 4 to get the total size. */ sz.side1 *= 4; sz.side2 *= 4; @@ -426,12 +426,12 @@ static void northbridge_set_registers(void) u16 value; int igd_memory = 0; - printk(BIOS_DEBUG, "Setting initial Nothbridge registers....\n"); + printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n"); /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); - /* Set the value for Programable Attribute Map Registers + /* Set the value for Programmable Attribute Map Registers * Ideally, this should be R/W for as many ranges as possible. */ pci_write_config8(NORTHBRIDGE, PAM0, 0x30); |