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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
| commit | d773fd370a92a6da2f7dbf91c085eb0df1f6f30d (patch) | |
| tree | fdaa9bd6278f4772c318d105e92a7cfdbc884521 /src/northbridge/intel/i82830 | |
| parent | 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (diff) | |
| download | coreboot-d773fd370a92a6da2f7dbf91c085eb0df1f6f30d.tar.xz | |
Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i82830')
| -rw-r--r-- | src/northbridge/intel/i82830/raminit.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/i82830/raminit.h | 3 |
2 files changed, 6 insertions, 9 deletions
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c index 8d75c42189..f96306e2d1 100644 --- a/src/northbridge/intel/i82830/raminit.c +++ b/src/northbridge/intel/i82830/raminit.c @@ -101,16 +101,16 @@ static void initialize_dimm_rows(void) switch (row) { case 0: - device = DIMM_SPD_BASE; + device = DIMM0; break; case 1: - device = DIMM_SPD_BASE; + device = DIMM0; break; case 2: - device = DIMM_SPD_BASE + 1; + device = DIMM0 + 1; break; case 3: - device = DIMM_SPD_BASE + 1; + device = DIMM0 + 1; break; } @@ -224,7 +224,7 @@ static void set_dram_row_boundaries(void) for (i = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; drb1 = 0; drb2 = 0; @@ -316,7 +316,7 @@ static void set_dram_row_attributes(void) for (i = 0; i < DIMM_SOCKETS; i++) { unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; /* First check if a DIMM is actually present. */ if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h index 3b4bf5fb2e..f54409bf4e 100644 --- a/src/northbridge/intel/i82830/raminit.h +++ b/src/northbridge/intel/i82830/raminit.h @@ -27,7 +27,4 @@ /* The 82830 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 -/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ -#define DIMM_SPD_BASE 0x50 - #endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */ |