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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:05:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:28:48 +0200 |
| commit | 15279a9696c70b82c2223264a505da9122f9aa7b (patch) | |
| tree | 7038d85ab02e392f86a618c49f3db31e14d250f0 /src/northbridge/intel/i855 | |
| parent | 585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (diff) | |
| download | coreboot-15279a9696c70b82c2223264a505da9122f9aa7b.tar.xz | |
src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/i855')
| -rw-r--r-- | src/northbridge/intel/i855/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i855/raminit.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index aba19663bb..e9b1cac996 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 63ee98b46a..478966308c 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -878,7 +878,7 @@ static void spd_update(u8 reg, u32 new_value) #endif } -/* if ram still doesn't work do this function */ +/* if RAM still doesn't work do this function */ static void spd_set_undocumented_registers(void) { spd_update(0x74, 0x00000001); |