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authorEric Biederman <ebiederm@xmission.com>2004-10-21 10:44:08 +0000
committerEric Biederman <ebiederm@xmission.com>2004-10-21 10:44:08 +0000
commitdbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d (patch)
treee813d3f9dea80d35cbc29d6bf35995fec0a06ab9 /src/northbridge/intel/i855pm
parentf3aa4707d3bef9f529a70a204dbc648968cf7c20 (diff)
downloadcoreboot-dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d.tar.xz
- Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i855pm')
-rw-r--r--src/northbridge/intel/i855pm/chip.h2
-rw-r--r--src/northbridge/intel/i855pm/northbridge.c33
2 files changed, 2 insertions, 33 deletions
diff --git a/src/northbridge/intel/i855pm/chip.h b/src/northbridge/intel/i855pm/chip.h
index 46b4a68265..3f6921f2ee 100644
--- a/src/northbridge/intel/i855pm/chip.h
+++ b/src/northbridge/intel/i855pm/chip.h
@@ -2,4 +2,4 @@ struct northbridge_intel_i855pm_config
{
};
-extern struct chip_control northbridge_intel_i855pm_control;
+extern struct chip_operations northbridge_intel_i855pm_control;
diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c
index f980c5436a..b43a853eee 100644
--- a/src/northbridge/intel/i855pm/northbridge.c
+++ b/src/northbridge/intel/i855pm/northbridge.c
@@ -113,38 +113,7 @@ struct mem_range *sizeram(void)
return mem;
}
-static void enumerate(struct chip *chip)
-{
- extern struct device_operations default_pci_ops_bus;
- chip_enumerate(chip);
- chip->dev->ops = &default_pci_ops_bus;
-}
-#if 0
-static void northbridge_init(struct chip *chip, enum chip_pass pass)
-{
-
- struct northbridge_intel_i855pm_config *conf =
- (struct northbridge_intel_i855pm_config *)chip->chip_info;
-
- switch (pass) {
- case CONF_PASS_PRE_PCI:
- break;
-
- case CONF_PASS_POST_PCI:
- break;
-
- case CONF_PASS_PRE_BOOT:
- break;
-
- default:
- /* nothing yet */
- break;
- }
-}
-#endif
-struct chip_control northbridge_intel_i855pm_control = {
- .enumerate = enumerate,
-// .enable = northbridge_init,
+struct chip_operations northbridge_intel_i855pm_control = {
.name = "intel i855pm Northbridge",
};