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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 20:37:21 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:45:36 +0000 |
commit | dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 (patch) | |
tree | eb17076271066e5c271742227f76720b28da6d16 /src/northbridge/intel/i945/Makefile.inc | |
parent | bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31 (diff) | |
download | coreboot-dc584c3f221bb59ee6b89e5517617b9d1d74bcf3.tar.xz |
nb/intel/i945: Move boilerplate romstage to a common location
This adds callbacks for mainboard specific init.
Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/Makefile.inc')
-rw-r--r-- | src/northbridge/intel/i945/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index af3c23580c..585d61b218 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c +romstage-y += romstage.c romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c |