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author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-30 17:16:51 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2020-04-11 09:19:13 +0000 |
commit | 3dff32c8041bb6d1ee4b2c5a8681ec0259b46bf6 (patch) | |
tree | d0207b25eee58f16bb5a8c222f4798278b15fcee /src/northbridge/intel/i945/bootblock.c | |
parent | fd8de1860df9487cffb62bb2b657bd6e55b20596 (diff) | |
download | coreboot-3dff32c8041bb6d1ee4b2c5a8681ec0259b46bf6.tar.xz |
nb/i945: Improve code formatting
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i945/bootblock.c')
-rw-r--r-- | src/northbridge/intel/i945/bootblock.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index d1cf6db17d..edc2170493 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -10,16 +10,13 @@ void bootblock_early_northbridge_init(void) uint32_t reg; /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. - * That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the PCIEXBAR + * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit + * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final assumption is that + * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. + * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); |