diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-06-11 14:13:33 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-22 14:51:39 +0000 |
commit | 3580d816e6d7a08434d91e9e1acdb94a47f07836 (patch) | |
tree | 05f09f89f19c110c9c05078eb82852d160f0af5b /src/northbridge/intel/i945/early_init.c | |
parent | ce55b36c999a0d7c9e47418f81df4566a813670d (diff) | |
download | coreboot-3580d816e6d7a08434d91e9e1acdb94a47f07836.tar.xz |
nb/intel/i945: Put names to northbridge PCI devices
Tested with BUILD_TIMELESS=1, Getac P470 does not change.
Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
-rw-r--r-- | src/northbridge/intel/i945/early_init.c | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a8c160a22d..b04a2f5940 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -15,7 +15,7 @@ int i945_silicon_revision(void) { - return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); + return pci_read_config8(HOST_BRIDGE, PCI_CLASS_REVISION); } static void i945m_detect_chipset(void) @@ -23,7 +23,7 @@ static void i945m_detect_chipset(void) u8 reg8; printk(BIOS_INFO, "\n"); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; switch (reg8) { case 1: printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); @@ -46,7 +46,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, " Chipset\n"); printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0xe0) >> 5; switch (reg8) { case 2: printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ @@ -63,7 +63,7 @@ static void i945m_detect_chipset(void) printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "(G)MCH capable of "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); switch (reg8) { case 2: printk(BIOS_DEBUG, "up to DDR2-667"); @@ -89,8 +89,8 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "\nIntel(R) "); - reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) - | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); + reg8 = ((pci_read_config8(HOST_BRIDGE, 0xe7) >> 5) & 4) + | ((pci_read_config8(HOST_BRIDGE, 0xe4) >> 4) & 3); switch (reg8) { case 0: case 1: @@ -116,7 +116,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, " Chipset\n"); printk(BIOS_DEBUG, "(G)MCH capable of "); - reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); + reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); switch (reg8) { case 0: case 2: @@ -144,10 +144,10 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); /* vram size from CMOS option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) @@ -155,25 +155,25 @@ static void i945_setup_bars(void) /* make sure no invalid setting is used */ if (gfxsize > 6) gfxsize = 2; - pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); + pci_write_config16(HOST_BRIDGE, GGC, ((gfxsize + 1) << 4)); /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config32(HOST_BRIDGE, 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -245,7 +245,7 @@ static void i945_setup_egress_port(void) } /* Is internal graphics enabled? */ - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) MCHBAR32(MMARB1) |= (1 << 17); /* Assign Virtual Channel ID 1 to VC1 */ @@ -405,7 +405,7 @@ static void i945_setup_dmi_rcrb(void) #endif DMIBAR32(0x204) = reg32; - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { printk(BIOS_DEBUG, "Internal graphics: enabled\n"); DMIBAR32(0x200) |= (1 << 21); } else { @@ -501,7 +501,7 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); - pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0); + pci_or_config16(HOST_BRIDGE, DEVEN, DEVEN_D1F0); pci_and_config32(p2peg, PEGCC, ~(1 << 8)); @@ -600,9 +600,9 @@ static void i945_setup_pci_express_x16(void) if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); reg16 = (1 << 1); - pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); + pci_write_config16(HOST_BRIDGE, GGC, reg16); - pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); + pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); } /* Enable GPEs: PMEGPE, HPGPE, GENGPE */ @@ -698,7 +698,7 @@ disable_pciexpress_x16_link: printk(BIOS_DEBUG, "ok\n"); /* Finally: Disable the PCI config header */ - pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0); + pci_and_config16(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0); } static void i945_setup_root_complex_topology(void) @@ -738,7 +738,7 @@ static void i945_setup_root_complex_topology(void) DMIBAR32(DMILE2A) = DEFAULT_EPBAR; /* PCI Express x16 Port Root Topology */ - if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { + if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); pci_or_config32(p2peg, LE1D, 1 << 0); } @@ -777,7 +777,7 @@ static void ich7_setup_pci_express(void) void i945_early_initialization(void) { /* Print some chipset specific information */ - switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { + switch (pci_read_config32(HOST_BRIDGE, 0)) { case 0x27708086: /* 82945G/GZ/GC/P/PL */ i945_detect_chipset(); break; |