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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 23:48:42 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:46:18 +0000 |
commit | c583920a748fb8bd7999142433ad08641b06283d (patch) | |
tree | ac67268b34fed71bbf5f2915e6da0860151e60ee /src/northbridge/intel/i945/i945.h | |
parent | e27c013f39f0433dac57a754b3484553a536f30d (diff) | |
download | coreboot-c583920a748fb8bd7999142433ad08641b06283d.tar.xz |
nb/intel/i945: Initialize console in bootblock
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
-rw-r--r-- | src/northbridge/intel/i945/i945.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index e9e6f4d094..82f80ff725 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -378,8 +378,6 @@ u32 decode_tseg_size(const u8 esmramc); /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); -/* Optional: Initialize the superio for serial output. */ -void mainboard_superio_config(void); /* Optional: mainboard specific init after console init and before raminit. */ void mainboard_pre_raminit_config(int s3_resume); /* Mainboard specific RCBA init. Happens after raminit. */ |