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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-01-19 12:52:25 +0100 |
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committer | Martin Roth <martinroth@google.com> | 2018-01-23 05:19:31 +0000 |
commit | 8324d87bf4f8900971be5584f11110dc261f14e5 (patch) | |
tree | 41201a80178b2977e178a8d84c25702206821483 /src/northbridge/intel/i945/northbridge.c | |
parent | 36e809ffd61f39da657023e3a7278616ecc4dfb7 (diff) | |
download | coreboot-8324d87bf4f8900971be5584f11110dc261f14e5.tar.xz |
nb/intel/i945: Use ESMRAMC instead of 0x9e
Macro renamed to be in accordance with the name used in the datasheet.
Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/i945/northbridge.c')
-rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 57f4388506..fdb37b1d47 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -95,7 +95,7 @@ static void pci_domain_set_resources(device_t dev) uma_memory_size = uma_size * 1024ULL; } - reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); + reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), ESMRAMC); if (reg8 & 1) { int tseg_size = 0; printk(BIOS_DEBUG, "TSEG decoded, subtracting "); |