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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 12:57:42 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-03 10:18:14 +0000 |
commit | cf3076eff17dc9c152fca6ec9012e7734ff88b4c (patch) | |
tree | ca4fd543bd87f02b3ff0e001ceca30c9c94c2f03 /src/northbridge/intel/i945/northbridge.c | |
parent | 6af3e6f4ff2ff727fec3034ef64c6dd604d44c9c (diff) | |
download | coreboot-cf3076eff17dc9c152fca6ec9012e7734ff88b4c.tar.xz |
nb/intel/i945: Use common SMM_TSEG code
Use the common SMM_TSEG code to relocate the smihandler to TSEG.
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel d945gclf and Lenovo Thinkpad X60.
Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/northbridge.c')
-rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index bec0c58d9b..ef3c59cb72 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -24,6 +24,7 @@ #include <string.h> #include <cpu/cpu.h> #include <arch/acpi.h> +#include <cpu/intel/smm/gen1/smi.h> #include "i945.h" static int get_pcie_bar(u32 *base) @@ -154,6 +155,36 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } +void northbridge_write_smram(u8 smram) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (dev == NULL) + die("could not find pci 00:00.0!\n"); + + pci_write_config8(dev, SMRAM, smram); +} + +/* + * Really doesn't belong here but will go away with parallel mp init, + * so let it be here for a while... + */ +int cpu_get_apic_id_map(int *apic_id_map) +{ + unsigned int i; + + /* Logical processors (threads) per core */ + const struct cpuid_result cpuid1 = cpuid(1); + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + + /* TODO in parallel MP cpuid(1).ebx */ + for (i = 0; i < cores; i++) + apic_id_map[i] = i; + + return cores; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. |