diff options
| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2017-02-22 18:46:27 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-22 22:47:28 +0100 |
| commit | bce7e33f234a498d7437f2677eff0084f540fd15 (patch) | |
| tree | 77f857aec1a5de3df095e0b9e115d34d2fd50706 /src/northbridge/intel/i945/raminit.c | |
| parent | b29e0b70f856f699d60c219eedf4d9b4146154cb (diff) | |
| download | coreboot-bce7e33f234a498d7437f2677eff0084f540fd15.tar.xz | |
intel/i945: Fix up whitespace and indentation
Fix up the whitespace issues introduced in commit 39bfc6cb
(nb/i945/raminit.c: Fix dll timings on 945GC).
Change-Id: I3a4152866226401bc51c7fb1752aab541a4c72b0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18465
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel/i945/raminit.c')
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8fe5f249df..a8bb5e7d1c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1238,15 +1238,15 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ + case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ + case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ + case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ + case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ } } @@ -1258,7 +1258,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; - } + } } } |