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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 23:48:42 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:46:18 +0000 |
commit | c583920a748fb8bd7999142433ad08641b06283d (patch) | |
tree | ac67268b34fed71bbf5f2915e6da0860151e60ee /src/northbridge/intel/i945/romstage.c | |
parent | e27c013f39f0433dac57a754b3484553a536f30d (diff) | |
download | coreboot-c583920a748fb8bd7999142433ad08641b06283d.tar.xz |
nb/intel/i945: Initialize console in bootblock
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel/i945/romstage.c')
-rw-r--r-- | src/northbridge/intel/i945/romstage.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index c11a78ab0e..479588129d 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -28,10 +28,6 @@ __weak void mainboard_lpc_decode(void) { } -__weak void mainboard_superio_config(void) -{ -} - __weak void mainboard_pre_raminit_config(int s3_resume) { } @@ -51,12 +47,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - i82801gx_lpc_setup(); mainboard_lpc_decode(); - mainboard_superio_config(); - - /* Set up the console */ - console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { system_reset(); |