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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 16:18:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:44:14 +0000 |
| commit | a402a9e7ab4ce46bc8829646e59cffa079309590 (patch) | |
| tree | 28c18f21b871149d055c0dbb4627fec6eb7cb610 /src/northbridge/intel/i945 | |
| parent | 20f71369d95d9691e668455b2262c80997fc8c3f (diff) | |
| download | coreboot-a402a9e7ab4ce46bc8829646e59cffa079309590.tar.xz | |
nb/intel/x4x: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Intel DG41WV, the stage cache gets properly created and used
on S3 resume.
Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945')
0 files changed, 0 insertions, 0 deletions